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? semiconductor components industries, llc, 2002 march, 2002 rev. 6 1 publication order number: mc33565/d mc33565 smart voltage regulator for peripheral card applications the mc33565 low drop out voltage regulator is designed for computer peripheral card applications, allowing glitchfree transitions from asleepo to aactiveo system modes. it has internal logic circuitry to detect whether there is a 5.0 v supply (aactiveo system mode) or an auxiliary 3.3 v supply (asleepo system mode). a guaranteed 3.3 v regulated output voltage at 200 ma is always available even if the main 5.0 v supply drops out. the regulated 3.3 v output voltage is provided by either an internal low dropout voltage regulator or an external pchannel mosfet switch, depending on the system being in the aactiveo or asleepo mode. features ? glitchfree transition from asleepo to aactiveo mode ? compatible with instantly available pc systems ? output current up to 200 ma ? output regulated to 2% over temperature ? excellent line and load regulation (0.4%) ? prevents reverse current flow during sleep mode ? short circuit protection applications ? computer ? ethernet ? pci/nic cards figure 1. simplified block diagram low voltage detector reference regulator 3.3 v/200 ma 3.3 v 5.0 v main input auxiliary input switch drive regulator output sense input ground d s g load external pchannel mosfet 3.3 v http://onsemi.com pin connections device package shipping ordering information mc33565d soic8 98 units / rail pins 2 and 5 are not internally connected mc565 alyw mc33565dr2 soic8 2500 / tape & reel 1 8 soic8 d suffix case 751 marking diagrams a = assembly location l = wafer lot y = year w = work week 18 5 3 4 main input auxiliary input switch drive 7 6 2 regulator output nc gnd nc sense input 1 8 micro8 (msop8) dm suffix case 846a m565 alyw mc33565dmr2 micro8 2500 / tape & reel
mc33565 http://onsemi.com 2 figure 2. functional block diagram 1.25 v reference 3.3 v 5.0 v main input auxiliary input switch drive regulator output sense input ground d s g load 3 1 4 + 4.7 f 7 6 8 - + - + low voltage detector 23.1 k 10.4 k 3.3 v regulator 475 289 thermal shutdown 4.02 v/ 4.17 v current sense external pchannel mosfet 3.3 v pin assignments and functions pin # function pin description 1 main input this input connects to the system main power source, typically 5.0 v. 2, 5 nc no connection. these pins are not internally connected. 3 auxiliary input this input connects to the system auxiliary power source, typically 3.3 v. 4 gnd this is the regulator and control circuit power ground. 6 sense input the sense input connects directly to the load allowing precise regulation. 7 regulator output this output is precisely regulated at 3.3 v and is capable of up to 200 ma. 8 switch drive this output is designed to drive the gate of an external pchannel mosfet switch.
mc33565 http://onsemi.com 3 maximum ratings (notes 1, 2) rating symbol value unit main input voltage range (pin 1) v in(m) 0.5 to +7.0 v auxiliary input voltage range (pin 3) v in(a) 0.5 to +7.0 v thermal resistance junction to air d suffix, soic8, case 751 dm suffix, msop8, case 846a r q ja 146 172 c/w operating junction temperature range t j 5.0 to +150 c storage temperature range t stg 55 to +150 c lead temperature (soldering, 10 seconds) t l 300 c electrical characteristics (v in(a) = 3.3 v, v in(m) = 5.0 v, pin 6 connected to pin 7, c pin6,7 = 4.7 f, for typical values t j = 25 c, for min/max values t j = 5.0 c to 150 c unless otherwise noted.) characteristic symbol min typ max unit main input (pin 1) operating voltage range v in(m) 4.3 5.0 5.5 v quiescent current (i o = 0 ma) i q(m) 8.0 10 ma output to input reverse leakage current (v in(m) = 0 v, v out = 3.5 v, t j = 25 c) i l 1.4 25 m a auxiliary input (pin 3) quiescent current (i o = 0 ma) i q(a) 1.9 3.0 ma regulator output (pin 7) output voltage (i o = 0 ma to 200 ma, note 3) v in(m) = 4.3 v to 5.5 v t a = 25 c t j = 5.0 c to 150 c v in(m) = v th(l) v in(m) = 7.0 v v out 3.267 3.234 3.0 3.1 3.3 3.3 3.3 3.333 3.366 3.5 v line regulation reg line 1.5 13.2 mv load regulation reg load 1.9 13.2 mv short circuit current (t j = 25 c, note 3) i sc 230 750 800 ma low voltage detector (pins 1, 8) input threshold voltage (figure 3) output low state transition, v in(m) decreasing output high state transition, v in(m) increasing hysteresis v th(l) v th(h) v h 3.9 0.120 4.02 4.17 0.150 4.3 4.3 0.180 v switch drive output (pin 8) output voltage low state (v in(m) = 0 v, v in(a) = 3.3 v, i sink = 200 a) high state (v in(m) = 5.0 v, v in(a) = 0 v, i source = 200 a) v o(l) v o(h) 3.4 0.044 4.15 0.2 v peak output current (c l = 1.2 nf) sink current (v in(m) = 3.9 v, v o = 1.0 v) source current (v in(m) = 4.3 v, v o = 2.3 v) i sink(pk) i source(pk) 15 15 22 39 ma propagation delay, main input to switch drive output (figure 4) c l = 1.2 nf switch drive output fall (v in(m) decreasing) switch drive output rise (v in(m) increasing) t dl t dh 0.65 1.4 3.5 3.5 s 1. maximum ratings are those values beyond which damage to the device may occur. 2. this device series contains esd protection and exceed the following tests: human body model 2500 v per mil std 883, method 3015. machine model method 400 v. 3. thermal shutdown activation can occur when the maximum operating junction temperature is exceeded.
mc33565 http://onsemi.com 4 typical characteristics figure 3. low voltage detector thresholds main input voltage 3.8 v v th(h) figure 4. switch drive to main input timing diagram 4.4 v 2.0 v 2.0 v v h v th(l) switch drive output main input voltage 3.8 v 4.4 v 2.0 v 2.0 v switch drive output t dh t dl v in(m) rise and fall times (10% to 90%) to be 100 m s. v in(m) rise and fall times (10% to 90%) to be 100 ns. figure 5. predicted gain and phase at zero load current figure 6. predicted gain and phase at full load current or gain (db) 0 frequency (hz) 100 200 phase margin 10 1 10 3 10 5 v out capacitor 5 m f 20 m esr v out capacitor 4.7 m f over operating temperature range. maximum esr permissible = 500 m over operating temperature range. or gain (db) 0 frequency (hz) 100 200 phase margin 10 1 10 3 10 5 v out capacitor 5 m f 20 m esr phase margin gain db 10 2 10 4 10 6 10 2 10 4 10 6 phase margin gain db
mc33565 http://onsemi.com 5 150 figure 7. switch drive output voltage high state (external pchannel mosfet turned off) vs. junction temperature t j , junction temperature ( c) 4.35 4.30 4.25 4.20 4.15 4.10 4.05 25 figure 8. switch drive output voltage low state (external pchannel mosfet turned on) vs. junction temperature t j , junction temperature ( c) 47 46 45 44 43 42 41 40 4.00 48 49 figure 9. switch drive peak output sink current vs. junction temperature t j , junction temperature ( c) 24.5 24.0 23.5 23.0 21.0 20.5 20.0 25 figure 10. switch drive peak output source current vs. junction temperature t j , junction temperature ( c) 39.0 38.5 38.0 37.5 37.0 36.5 19.5 39.5 figure 11. regulator output voltage vs. junction temperature t j , junction temperature ( c) 3.310 3.308 3.296 3.294 3.292 figure 12. line regulation vs. junction temperature t j , junction temperature ( c) 1.5 1.0 0.5 0 3.290 2.5 3.0 22.5 22.0 21.5 v in(m) = 5.0 v to 5.5 v v in(m) = 4.3 v v in(m) = 5.0 v v in(a) = 0 v i source = 200 m a v in(m) = 4.3 v to 5.5 v v out = 3.3 v i out = 200 ma i out = 200 ma i sink(pk) , switch drive peak output sink current (ma) v o(h) , switch drive output voltage high state (v) v in(m) = 0 v v in(a) = 3.3 v i sink = 200 m a v o(l) , switch drive output voltage low state (mv) v in(m) = 3.9 v v o = 1.0 v v in(m) = 4.3 v v o = 2.3 v v out , regulator output voltage (v) reg line , line regulation (mv) i source(pk) , switch drive peak output source current (ma) 0 25 50 75 100 125 150 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 40.5 40.0 41.0 3.302 3.300 3.298 3.306 3.304 2.0
mc33565 http://onsemi.com 6 2.5 1.0 0.5 3.0 3.5 figure 13. load regulation vs. junction temperature t j , junction temperature ( c) figure 14. main input quiescent current vs. junction temperature t j , junction temperature ( c) 8.0 7.8 7.6 7.4 7.2 7.0 0 8.2 8.4 figure 15. auxiliary input quiescent current vs. junction temperature t j , junction temperature ( c) 2.4 1.8 1.2 1.0 figure 16. output to input reverse leakage current vs. junction temperature t j , junction temperature ( c) 7 6 5 4 3 2 1 figure 17. low voltage detector lower threshold vs. junction temperature t j , junction temperature ( c) 4.024 4.020 4.016 4.012 3.996 0 4.028 1.6 1.4 4.008 4.004 4.000 v in(m) = 5.0 v v out = 3.3 v i out = 0 to 200 ma v in(m) = 5.0 v v in(a) = 0 v i out = 0 ma v in(m) = 0 v v in(a) = 3.3 v i out = 0 ma v in(m) = 0 v v out = 3.5 v i l measured at pin 1 reg load , load regulation (mv) i q(m) , main input quiescent current (ma) i q(a) , auxiliary input quiescent current (ma) i l , output to input leakage current ( m a) v th(l) , low voltage detector lower threshold (v) 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 2.0 2.2 2.0 1.5 figure 18. low voltage detector upper threshold vs. junction temperature t j , junction temperature ( c) 4.195 4.185 4.165 4.155 4.145 4.135 4.125 v th(h) , low voltage detector upper threshold (v) 25 0 25 50 75 100 125 150 4.175 v in(m) decreasing v in(m) increasing
mc33565 http://onsemi.com 7 regulator output figure 19. switch drive output rise time vs. junction temperature t j , junction temperature ( c) 1.35 1.30 1.25 1.65 1.60 1.55 1.50 1.45 1.40 figure 20. switch drive output fall time vs. junction temperature t j , junction temperature ( c) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 figure 21. bypass mode transition 0 figure 22. load transient response trace 1: v in(m) stepping from 5 v to v th(l) trace 2: v out switching from regulator output to v in(a) v out switching to bypass mode ch1 ch2 100 mv/div 1.00 v/div 20.0 s/div v in(m) falling to v th(l) v in(a) via bypass mode fet trace 1 trace 2 v out load transient response no load 200 ma load trace 1 trace 2 t dl , switch drive output fall time ( m s) t dh , switch drive output rise time ( m s) 25 0 25 50 75 100 125 150 25 0 25 50 75 100 125 150 c l = 1.2 nf c l = 1.2 nf
mc33565 http://onsemi.com 8 operating description the mc33565 is designed for power managed computer applications such as peripheral card interface (pci) and network interface cards (nic) where glitchfree transitions between 3.3 v and 5.0 v supplies are necessary. in this type of application, the presence of a 5.0 v supply represents the aactiveo system mode, while the presence of 3.3 v represents the asleepo system mode. the mc33565 complies with the instantly available requirements as specified by the advanced configuration and power interface (acpi) standards set by intel, microsoft, and toshiba. a regulated output voltage of 3.3 v is available even when the 5.0 v supply has been shut down and only the 3.3 v auxiliary supply is available. the mc33565 has two supply inputs, the main input (typically 5.0 v) and an auxiliary input (typically 3.3 v). the mc33565 functions as a linear regulator while the main input is greater than its lower threshold voltage. below this threshold, the internal regulator turns off and the 3.3 v output is supplied from the auxiliary input via the external pchannel mosfet. the pchannel mosfet gate is controlled by the switch drive output. low voltage detector internal circuitry detects if the system is being powered from the main or the auxiliary input supply. during normal operating conditions, the mc33565 is powered by the main input. a regulated output voltage of 3.3 v is provided by an internal low drop out 5.0 v to 3.3 v voltage regulator. while in this mode, the gate of the pchannel mosfet is driven high, turning the mosfet switch off. the internal low voltage detector has typical upper and lower thresholds of 4.17 v and 4.02 v, respectively. the typical hysteresis voltage between the upper and lower thresholds is 150 mv, providing good noise immunity. if the main input supply is not available or the supply voltage drops below the 4.02 v, the internal regulator turns off and the switch drive goes low. this enables the external mosfet switch, connecting the 3.3 v auxiliary supply to the l oad allowing the load to remain powered even though the main input supply is not available. once the main input supply voltage is above 4.17 v, the mosfet switch drive goes high and the internal regulator is enabled. the low voltage detector logic is active throughout the entire range of the main input supply ramp up. the switch drive signal is never turned on or off inappropriately during the main input ramp up. the output voltage is kept above 3.0 v while the load is biased from the main input supply. input blocking the internal regulator pass device (npn transistor) ensures that no significant reverse current flows from v out to the main supply or gnd while the output is powered by the auxiliary supply. reverse current is typically less than 6.0 a over the entire operating temperature range. pchannel mosfet switch polarity the pchannel mosfet drain should be connected to the auxiliary input, the source to the load and the gate to the switch drive output. it is imperative that the polarity of the pchannel mosfet is not reversed. if it is reversed, that is the drain connected to the load and the source connected to the auxiliary supply, the body diode could be forward biased if the auxiliary supply voltage is below v out . consequently, the linear regulator would not turn off and it would supply current to the auxiliary supply rail. external compensation regulators are in nature feedback systems. as with any feedback system, loop stability needs to be evaluated to insure stability. the mc33565 requires an external compensation capacitor with a minimum value of 4.7 f for stability. increasing the capacitance will improve the overall load transient response. the equivalent series resistance (esr) of the capacitor should be less than 0.5 in order for the output voltage to be maintained within tight tolerance. sense the sense input provides tight regulation of the output voltage while the main supply is present even with varying load current. to take the most benefit of the sense input, connect pin 6 as close as possible to the load. use a separate trace to connect the source of the mosfet switch to the load as shown in figure 23. this will help reduce interference or coupling in the sense input generated by the output current. the use of the sense input is required for correct device operation. sense input v in(a) figure 23. voltage regulation using sense feature r l switch drive output 6 7 8 d s g regulator output 4.7 f board layout it is recommended that the mc33565 is placed as close as possible to the mosfet switch and compensation capacitor. use short traces to minimize extraneous signals from being induced in the sense input or switch drive signals. also, avoid routing the sense input close to the input and load current paths, as well as the ground return path to prevent signal coupling. the part list and board layout for a demonstration board using the mc33565 in an soic8 package are available. the board operates with an input voltage between 4.3 v and
mc33565 http://onsemi.com 9 5.5 v and provides an output current up to 200 ma. the demonstration board layout (silk screen and top layers) are shown in figures 26 and 27, respectively. current limit and thermal shutdown the mc33565 incorporates current limit and thermal shutdown to protect the device during fault conditions. if the device detects a current limit or short circuit condition, typically 730 ma, the device limits the drive to the internal regulator. thermal shutdown protects the internal circuitry in the event that maximum junction temperature is exceeded. when activated, typically at 170 c, the output is disabled. there is no hysteresis built into the thermal limiting circuit. as a result, if the device is overheating, the output will appear to be oscillating. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a substitute for proper heatsinking. please consider that the thermal resistance values provided in the maximum ratings table will vary depending on pad size, adjacent components and air flow. if you are planning to operate the device close to its maximum junction temperature it is recommended that you measure the device temperature in your application to insure junction temperature is not exceeded. motherboard/ mainboard pci slot main input nc auxiliary input gnd drive output regulator output sense input nc 1 2 3 4 8 7 6 5 mc33565 pci nic card circuitry 5 v 3.3 v c1 0.1 m f c3 0.1 m f c2 10 m f c5 0.1 m f c4 10 m f main input nc nc gnd drive output regulator output sense input nc 1 2 3 4 8 7 6 5 mc33565 10 m f 50 m f 2 k 2 k 4.7 m f 5 v or 3.3 v input v out 3 5, 6 4 1 7, 8 2 p/2 n/2 figure 24. application board schematic (see figures 26 and 27) figure 25. alternative application: 5.0 v or 3.3 v card input with hot swap circuitry d s g mtdf1c02hd mgsf1p02elt
mc33565 http://onsemi.com 10 5 v in 18 45 sense v out cut here to enable gnd v aux remote sense c2 c3 q1 c4 c5 c1 u1 figure 26. demonstration board silk screen layer figure 27. demonstration board top layer parts list qty reference part/description vendor notes 3 c1, c3, c5 0.1 m f ceramic capacitor various 2 c2, c4 10 m f tantalum capacitor various 1 u1 mc33565d on semiconductor (soic8 only) 1 q1 mgsf1p02elt on semiconductor pchannel mosfet
mc33565 http://onsemi.com 11 package dimensions soic8 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m micro8 (msop8) dm suffix case 846a02 issue e s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l
mc33565 http://onsemi.com 12 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33565/d micro8 is a trademark of international rectifier. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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